1. Field of the Invention
The present invention relates to a semiconductor memory device and a connecting method of a sense amplifier, and more particularly to a connecting method of a sense amplifier, which is capable of achieving high integration of a semiconductor memory device by optimizing a method of connecting bit lines and complementary bit lines of a memory cell array to the sense amplifier, and a semiconductor memory device using the same.
2. Description of the Related Art
With the development of computer systems and electronic communications, volatile semiconductor memory chips used for storage of information have become low-priced, miniaturized, and increased in their capacity. Particularly, the miniaturization of the memory chips has provided a basis of techniques for implementation of mass storage.
Recently, in addition to techniques for reducing the size of memory chips by optimizing the size and arrangement of memory cells, studies of miniaturization of the memory chips by simplifying peripheral circuits of the memory chips and reducing the number of signal lines have been actively conducted. The present invention has been conceived in view of these technical trends.
In general, a cell block for storing data of a dynamic random access memory (DRAM) device has a structure where a number of cells, each of which is composed of one n-type metal oxide silicon (NMOS) transistor and one capacitor, are respectively connected to word lines and bit lines, which are connected to each other in the form of matrix.
Hereinafter, operation of a general DRAM device will be briefly described.
First, when a /RAS signal, which is a main signal for operating the DRAM device, goes into an active state (low level), address signals are inputted to a row address buffer. Thereafter, the inputted address signals are decoded and a row decoding operation for selecting one of the word lines in the cell block is performed based on the decoded address signals.
At this time, when data of cells connected to the selected word line is loaded on a pair of bit lines BL and /BL, which is composed of a bit line and a complementary bit line, a signal indicating a time-point of operation of a sense amplifier is enabled to drive a sense amplifier driving circuit in a cell block selected by the address signal. In addition, sense amplifier bias potentials are shifted to a core potential Vcore and a ground potential Vss, respectively, to drive the sense amplifier. When the sense amplifier begins to be operated, a minute potential difference which is being maintained by the pair of bit lines BL and /BL is shifted to a large potential difference, and thereafter, a column decoder selected by a column address turns on a column transfer transistor for transferring data loaded on the pair of bit lines BL and /BL to a pair of data bus lines DB and /DB through which the data is outputted to the outside of the DRAM device.
More specifically, in the operation as described above, the pair of bit lines BL and /BL is pre-charged to ½ Vcc in a standby mode before the DRAM device begins to be operated. Thereafter, when the DRAM device is operated, data of the cells is loaded on the pair of bit lines BL and /BL. Accordingly, the pair of bit lines BL and /BL has a minute potential difference there between. In this state, when the sense amplifier begins to be operated to amplify potentials of the pair of bit lines BL and /BL, such that the pair of bit lines BL and /BL which maintain the minute potential difference there between has the core potential Vcore and the ground potential Vss, respectively. Data on the pair of bit lines BL and /BL having the amplified potentials, i.e., the potential Vcore and the ground potential Vss, is transferred to the pair of data bus lines DB and /DB.
Hereinafter, a conventional connecting method of the sense amplifier, operation of the sense amplifier, and related problems will be described with reference to FIG. 1.
In general, the semiconductor memory device, particularly, the DRAM, includes a memory cell array including a plurality of word lines xWLy connected respectively to a plurality of memory cell blocks, each of which is composed of a plurality of memory cells, in a row direction of the memory cells, and a plurality of pairs of bit lines, each of which is composed of a bit line xBLy and a complementary bit line x/Bly, connected respectively to the plurality of memory cell blocks in a column direction of the memory cells; and a plurality of sense amplifier arrays, each of which includes a plurality of sense amplifiers xSAy, each of which is connected to the bit line xBLy and the complementary bit line x/BLy, for sensing a potential difference between the bit line xBLy and the complementary bit line x/Bly.
Where, ‘x’ and ‘y’ are random numbers, ‘x’ in the word lines xWLy indicates an x-th memory cell block from top to bottom of the memory cell arrays, ‘y’ in the word lines xWLy indicates a word line at a y-th row from top of bottom of the memory cell blocks, ‘x’ in the bit line xBLy and the bit line x/BLy indicates an x-th memory cell block from top to bottom of the memory cell arrays, and ‘y’ in the bit line xBLy and the bit line x/BLy indicates a bit line or a complementary bit line at a y-th column from left to right of the memory cell blocks. In addition, ‘x’ in the sense amplifiers xSAy indicates a sense amplifier of an x-th sense amplifier array from top to bottom of the memory cell arrays, and ‘y’ in the sense amplifier xSAy indicates a y-th sense amplifier from left to right of the sense amplifier arrays.
As shown in FIG. 1, in the conventional semiconductor memory device, the sense amplifiers are connected to the pairs of bit lines of respective memory cell blocks, which are adjacent above and below the sense amplifiers. For example, in FIG. 1, a sense amplifier 2SA1 is connected to a pair of bit lines 1BL2 and 1/BL2 of an adjacent upper memory cell block 100 and a pair of bit lines 2BL2 and 2/BL2 of an adjacent lower memory cell block 200.
FIG. 2 is a circuit diagram of a portion 10 indicated by a dotted line. Now, sensing and amplifying operation of the conventional sense amplifier will be described with reference to FIG. 2.
Referring to FIG. 2, if a voltage charge-shared by a bit line 1BL2 and a complementary bit line 1/BL2 is to be sensed, NMOSs N12 and N1/2, which are a switching device, are turned on by applying control signals bis12 and bis1/2 of high level to gate electrodes of the NMOSs N12 and N1/2, respectively, such that only the pair of bit lines is selected. At this time, other switching devices except the NMOSs N12 and N1/2 are turned off by applying control signals of low level to gate electrodes of other switching devices in order to prevent charges from being introduced from pairs of bit lines to other switching devices.
Next, a sense amplifier 2SA1 senses data of memory cells transferred to the pair of bit lines 1BL2 and 1/BL2 and amplifies the sensed data to full-logic level. More specifically, if a level of the data transferred from the bit line 1BL2 is sensed to have a high level, an NMOS N2 is turned on, and accordingly, a potential at a node B is shifted to a ground potential Vss. This ground potential Vss at the node B is applied to a gate of a PMOS P1, thus turning on the PMOS P1. Accordingly, a potential at a node A is shifted from a high level to a core potential Vcore level. On the contrary, if the level of the data transferred from the bit line 1BL2 is sensed to have a low level, a PMOS P2 is turned on, and accordingly, the potential at the node B is shifted to the core potential Vcore. This core potential Vcore at the node B is applied to a gate of an NMOS N1, thus turning on the NMOS N1. Accordingly, the potential at the node A is shifted from a low level to a ground potential Vss level.
In addition, if a voltage charge-shared by a pair of bit lines 2BL2 and 2/BL2 is to be sensed, NMOSs N22 and N2/2 are tuned on by applying control signals bis22 and bis2/2 of high level to gate electrodes of the NMOSs N22 and N2/2, and thereafter, the same operation as described above is performed.
However, the conventional connecting method of the sense amplifier and the semiconductor memory device using the same method have a problem of going against the technical trend toward high integration. Namely, since the conventional sense amplifier performs a sensing operation in charge of only adjacent upper and lower memory cell blocks, there is a problem in that a large number of sense amplifiers are required, and accordingly, an area occupied by sense amplifiers in a memory chip becomes large. Accordingly, as the overall size of the memory chip increases, there arises a problem of going against the trend of semiconductor memory techniques to accomplish low-price, high integration, and high-capacity semiconductor memory devices.